Magic to get things working

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LVS

Before starting Calibre LVS choose in Virtuoso window:

- Calibre -> Setup -> Netlist Export ...

In the pop-up window insert in the field 'Include':

- <Your TSMC90nm run path>/Calibre/lvs/source_added

Hit 'OK'


Then start Calibre LVS by:

- Calibre -> Run LVS


Set rules file (annoyingly each time you start):

- Choose the 'Rules' button

- Browse for rules file by hitting the '...' button

- select <Your TSMC90nm run path>/Calibre/lvs/calibre.lvs


Tell LVS to get the schematics netlist from the schematics (annoyingly each time you start):

- Choose the 'Inputs' button on the left

- Choose the 'Netlist' flag

- Activate 'Export from schematic viewer' toggle button


DRC

Set rules file (annoyingly each time you start and different rules sets that all have to be tested):

- Chose - Choose the 'Rules' button

- Browse for rules file by hitting the '...' button

- select <Your TSMC90nm run path>/Calibre/drc/CMN90LP_1P9M_mini@sic.DRC (basic drc)

.ANT (antenna rules)

.MIM (MIM capacitor rules)

.BND (bonding pad rules, only for whole chip)


DRC errors that are only rlevant for the whole chip:

I have not figured out any way to turn them off. It seems the only way to deal with them is to ignore them at the risk of overlooking a relevant error in their midst. Typical errors irrelevant for individual cells are:

- CSR.* : ... is not allowed inside the empty area of chip corner.

- UTM.* : metal density rules

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