Cadence SPB

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Note that the Windows version of this tool is obsolete, and replaced by a newer Linux version. The following instruction/tutorial is not up to date, except for the startup procedure.

Cadence SPB is a relative comprehensive tool for design of PCBs. Below you will find a review of the most important processes to construct a finished PCB. All the aspects of the tool will not be described in this document. You can find complete documentation here:

This introduction is adapted to design of PCBs for production on our own PCB miller. But most of the content will be relevant for production through for instance Elprint.

  • /hom/mes/cadsoft/cadence/spb15.2/doc/
  • Allegro PCB Editor Tutorial /hom/mes/cadsoft/cadence/spb15.2/doc/algrotutorial/algrotutorialTOC.html
  • Allegro Design Entry HDL Tutorial /hom/mes/cadsoft/cadence/spb15.2/doc/concepthdl_tut/concepthdl_tutTOC.html


Contents


Startup

Create a new directory in your home directory.
Copy the following two files into this catalog:

/projects/nanos/script/SPB163/run
/projects/nanos/script/SPB163/.bash_spb163

Run the file 'run' to start the software.

Creation of project

  • Under the start menue choose Cadence SPB->Project Manager
    • Choose PCB Design Expert and press OK on Cadence Product Choises
  • Choose Create Design Project
    • Choose a name and folder for the project and press Next; In this guide the project is called wiki
  • Choose Add All--> and press Next
  • Under Library choose wiki_lib (the library name will be "'your chosen project name'_lib" in other projects) and choose an appropriate name for the PCB. Press Next; In this guide the PCB is called wikikort
    • If you have made a project in the same folder, there will not be made a new library for the project. Choose the library from the earlier project.
  • Press Finish

Define components

  • Choose Tools->Library Tools->Part Developer
  • In this guide we will define a Texas Instument SN7400 Quadruple 2-input NAND-gate with SOIC14-package
  • File->New->Cell
    • Choose wiki_lib and call the cell SN7400. Press OK
  • Right click on Symbols and choose New
  • Choose the Symbol Pins tab and press Pins->Add
    • The window Add Pin is opened
  • Fill in pins as described in the data sheet and illustrated under and press OK
    • NB: If you wish to add more pins at the same time, you can do this by setting number forfrom and to, but remember that:
      • name changes should be done inPins->Global Rename.
      • changing atribues should be done in Pins->Global Modify
      • If the names are changed in other places, it will lead to duplication of pins. This will give error messages and potential wron mapping. The duplicated pins will be visible from the tools under the Pins-button. Pins->Global Delete is used to delete pins

Image:PCBaddpin.jpg

  • Right click on Packages and choose New
  • In the Associated Footprint window, choose the browse button for Jedec Type
    • Choose SOIC14 and press OK
    • If the footprint does not exist in the list, you will have to draw it yourself. The way to do this is described in Tegning av footprint
  • Choose the Package Pin tab.
  • Press Footprint->Extract from Footprint and press Yes on the menu that pops up.
  • Press Pins->Add, and choose all the pins from the Add Pin window and press OK
  • Map all the pins as described in the data sheet an illustrated under
    • Choose one and one pin from each table an press Map:

Image:PCBmappin.jpg

    • You can do this by choosing all the pin numbers in the window Physical pins and all lines in the Logical Pins window and press Map.
      • NB: To map many pins you have to be sure that the sequence of the pins shown in both tables matches etch other. If this gets wrong the scheme will become wrong as you use the place/route tool later.
  • Location of pins in schema symbol (Tip: if you are going to do more advaced changes than what is described here, you should go out to project manager, choose file/change product and Librarian Expert while you handle symbols, and choose back to PCB design expert when you continues with schema and layout. When checking out the librarian-license gives you the possibility to see symbols and in some part footprint in part developer.)
    • In the tree menu on the left side, you choose sym_1 under symbols. Here the recipe for the look for the schema symbol for the komponent.
    • Choose the tab for symbol pins and turn of Preserve pin position (otherwise the pins wont follow the symbol edge when you change this)
    • Down to the left on the tab you will fint the box Symbol outline, the numbers you set in the text boxes Left, Right, Top and Bottom gives the size on the symbol in the schema after a routing a nett where a square normaly is the size of a letter (with kartesisian coordinates). To make the symbol easy to move in the schema, origin should be on the inside of the symbol. To make this happen you should choose negative values for Left and Bottom, and positive values for Right and Top. The difference between Bottom and Top should be four sizes larger than the numbers of pins; corresponding the difference between Left and Right should be about four sizes larger than the number of letters in the component name (possibly two sizes larger than the number of pins over or under). For SN7400 you can set for example:
      • Set Left to -5 and Right to 5 (10 in the with)
      • Set Top to 9 and Bottom to -9 (14 +4 = 18 in the hight)

Image:Symbol Pins.gif

    • Look in the table with the pins an set Location to the side of the symbol you wish to have on each of the pins
    • Set Position for each of the pins, respectively 6,4,2,0,2,4,6 for the pins on the left and right side. NB: Initially the schema symbols will always move two positions at the time, therefore all pins should be given even numbers, to avoid problems with wiering and to make the scema nice. Other than that the pin position in the schema symbol can be changed after what is practical, without creating problems in layout.
  • The component is finished defined
    • Choose File->Save
    • Control the design by right clicking on the symbol (sym_1 in the tree structure) and choose edit
      • Here is the symbol as it looks if you have followed the wiki:

Image:Skjemasymbol.gif

    • If you are not happy, go back to Part Developer and make changes and save again. To look at the symbol again, you can choose File->Revert in the symbol editor, this will reload the symbol.
      • NB: The symbol editor can also be used to move symbol name and pins, but this is not recommended to do on a large scale, as this can be rather ambiguous. Be aware of that changes over write what you work on in parts developer...
  • When the symbol is finished, you close both the symbol editor and Part Developer.

Schematics

  • Choose Design Entry
  • To add components, chosse Component->Add. Add two SN7400 from wiki_lib
  • Tip! Different mouse movements triggers certain commands:
    • z: zoom
    • m: move
    • c: copy
    • and so forth...
  • Choose Wire->Draw and draw a schmatic as illustrated below. (Note that this design has no function, but is intended as a description of a procedure)
  • Coose Wire->Signal Name to name a net. This has to be done for VCC and GND

Image:PCBdesignentry.jpg

  • Choose File->Save and File->Exit

Startup layout

  • Choose Layout (an error message will sometimes pop up, ignore this and press OK)
    • Choose Allegro PCB Design and press OK
  • Choose File->New
  • Write the name of the card, wikikort and choose Board (wizard) and press OK
    • Board Wizard opens and fill in as you wish. Beneath you will find an illustration of som usual choices.

Image:PCBboardwiz02.JPG

Image:PCBboardwiz03.jpg

Image:PCBboardwiz05.jpg

  • The smallest possible wire with is 0.2mm, but the recommended smallest is no less than 0.4mm.
  • When Board Wizard is finnished, save the layout and choose File->Exit

Export schematic

  • Choose Design Sync->Export Physical and fill out as illustrated under and press OK

Image:PCBexport.JPG

Layout

  • Open the layout as described above. Instead of making a new layout, wikikort is now automatically opened.
  • You find the components schematic by choosing Place->Manually
    • The Placement window is opend. Expand Components by refdes
  • Mark the cells U1 and U2 and place them in the layout.
  • You will now see that the logical connections are drawn between the components.
  • For multiple layered PCBs, the right VIA must be defined. Choose Tools->Padstack->Modify Library Padstack
  • Choose Hole0_9Mm from the list and press OK
  • Fill out the values as illustrated under.
    • Note that TOP, DEFAULT INTERNAL and BOTTOM layer is 0.8mm wider than the drill hole. This enshures that there is sufficient copper around the hole after milling. Use therefore always minimum 0.8mm distance between holes and TOP/BOTTOM

Image:PCBvia04.jpg

Image:PCBvia05.jpg

  • Save the modified edition as for instance VIA0_9mm and close the window
  • Choose Setup->Constraints and press Set values under Physical (lines/vias) rule set
  • Remove all vias first from Current via list and then only add 'VIA0_9mm to Current via list. Press OK twice
  • Choose Route->Connect (F6) and draw all the logical connections
    • Double click will make a via that switches between the two layers
    • To change collor on the routings so that they will be easier to separate top from bottom, choose Display->Color/Visibility
    • Make changes as for instance illustrated under and pressOK

Image:PCBcolorVisibility.jpg

Drawing Footprint

When you are going to define a , you should first check if there is available a suitable pad stack (A pad stack is the mounting point or the hole for the component). If this does not exist, you will have to make your own. This sektion will go through the procedure from defining the pad stack itself, to make the finished footprint. If the pad stack exists, you can proceed directly to Footprint

  • If the component is hole mounted, it can be necessary to monte a metal via after the milling to ensure contact between the layers. Figure 1 below illustrates this, while figure 2 shows when this is not necessary.
  • If a metal via is to be used, the diameter for the hole to the component pin must be increases by 0.4mm.

Image:PCBhull06.jpg


Image:PCBhull05.jpg


Padstack

  • Choose Layout
    • Choose Allegro PCB Design and press OK
  • Choose Tools->Padstack->Modify Library Padstack
  • Choose from the list the pad stack that resembles the most and press OK (NOTE: All numbers in MILS if nothing else is specified.)
    • In this guide there is made a rectangular pad stack with the measurements 2x0.5mm on the layer TOP
  • Fill in as illustrated below

Image:PCBmodpadstack02.jpg

Image:PCBmodpadstack01.jpg

  • Choose File->Save As and write a suitable name and placement, in this instance SMD2REC0_5mm.pad and M:\...\wiki\worklib\wikikort\physical
  • Choose Setup->User Preferences. Choose Design Paths and press the browser button for padpath. Add the catalog where you saved the padstack and press OK. Now your own defined pad stacks will be available from the menu. Note that this is only loaded during starup of Layout or Part Developer
  • Therefore choose File->Exit

Footprint

  • Choose Layout
    • Choose Allegro PCB Design and press OK
  • Choose File->New and write in the name for the foot print (In this guide the foot print name is qpl48)
  • Choose Package Symbol (wizard) and press OK
  • In the window Package Type, choose the correct package and press Next. If none of the alternatives is suitable choose the one that is nearest.
    • In this guid non fits, choose PLCC/QFP that is the one most equal.
  • Press Load Template and Next
  • Choose Units->Millimeter and Accuracy->3 and press Next
  • Fill in as specified in the data sheet.
    • Here some trail and error might be needed. It is not always easy to choose the right values. If you obviously has chosen wrong and the foot print does not fit, it is easiest to start the hole procedure over.
  • Choose Tools->PCB Editor Setup. Choose Design Paths and press the browser button for psmpath. Add the folder where you stored your footprint and press OK. Now your own defined foot prints will be choosable from the menu. Note that this is inly loaded during the startup of Layout or Part Developer
  • Choose therefor File->Exit

Generating Vdd/Gnd Plane

The PCB-miller works by isolating leading paths, pins and so forth from the rest of the copperon the card. This causes a finnished card to have large areas with floating copper. There is two ways to avoid this. Ether by removing all the floating copper or attach it to ether Vdd or Gnd. removing all excess copper is done by a separate tool, LPKFs CircuitCam, and can be done subsequent on the finished design. If excess copper is to be connected to Vdd or Gnd, this has to be done before Generering av filer for kretskortproduksjon. Then follow the steps below:

  • Choose Shape-> Polygon or Shape-> Rectangular
  • To the right in Active Class and Subclass, choose the desired layer, TOP or BOTTOM
    • For PCBs that is to be produced by Elprint, you have to choose Vdd or Gnd
  • To the right in Assign Net Name, choose the right nett name with the browse button.
    • A sensible choice here is Gnd
  • Then draw the area that is to be filled with the plane.
  • NB: If the plane you make does not stay away from the wires and holes, it can be wise to check Shape->Global Dynamic Shape Parameters->Shape fill->Dynamic fill: that should be smooth


Often this will generate a number of isolated islands. These can be removed in the following way:

  • Choose Shape-> Delete Islands
  • To the right there will now pop up some alternatives. Choose First to show the first island that has no connections to the rest of the plane. You can now choose to delete this by pressing Delete or leave it be and continue to the next one with Next.
  • Go through this procedure with each plane until all islands are removed.

You can also cut away some more of a plane, where for instance small structures between pins that can make soldering on a later stage difficult:

  • Choose Shape-> Manual Void-> Polygon or Shape-> Manual Void-> Rectangular
  • Draw an area that you wish to remove.
    • Pins and wires is not affected by this.

Add layers (multilayer)

  • Make sure that the PCB Design Expert license is chosen
    • In, Library Manager, choose File->Change Product and restart Allegro PCB Design if necessary
  • In Allegro PCB Design, choose Setup->Cross Section
    • A new window will open which displays the current layers
  • Click on the arrow to the left to either delete or insert a new layer
  • For a four layer PCB, define the different layers as shown in the illustration below

Image:PCBxsection01.jpg

Generating files for PCB production

  • Choose Manufacture->Artwork. Fill out as illustrated under and press Create Artwork. The files TOP.art and BOTTOM.art is made.

Image:PCBgenart01.jpg

Image:PCBgenart02.JPG

  • In the catalog ~/wiki/worklib/wikikort/physical, make a file wit the name nc_tools.txt and add:
0.6 P T0
0.7 P T1
0.8 P T2
0.9 P T3
1.0 P T4
1.1 P T5
1.3 P T6
1.5 P T7
2.0 P T8
2.4 P T9
3.0 P T10

  • Choose Manufacture->NC->NC Drill... and press NC Parameters... and fill out as illustrated below

Image:PCBgendrill01.jpg

  • Press Drill
    • If you get an error message during the generating of the drill file, then your design most likely contains drill holes with wrong diameter in regards to the tools described. in nc_tools.txt. An easy example illustrates what has to be done:
    • If the drill hole is more than 0.05mm from an available tool for instance 0.54mm, our PCB miller will ask for a drill with a diameter of 0.5mm. This does not exist and the design can not be produced. In this instance the padstack has to be changed so that the drill hole fits one of our tools. A natural choice would be 0.6mm.
    • If on the other hand the drill hole is 0.56mm, our PCB miller will interpret this hole as being a hole with a diametre of 0.6mm and the design can be produced. For the export of the drill holes to be correct, the nc_tools.txt has to look like this:
0.56 P T0
0.6 P T1
0.7 P T2
0.8 P T3
0.9 P T4
1.0 P T5
1.1 P T6
1.3 P T7
1.5 P T8
2.0 P T9
2.4 P T10
3.0 P T11
  • The files TOP.art, BOTTOM.art and wikikort*.drl can now be imported to CircuitCam and be made ready for production
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