Cadence-Tutorial-English-cadence 6.1.6

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This page will give an introduction to the use of Cadence 6.1.6 for RedHat 6 with the TSMC 90nm LowPower RF OpenAccess (TSMC90nmLPRFOA) design kit. The complete process from startup to simulating on layout will be presented for a inverter, the electronic version of a 'hello world' program. This is a long tutorial, so use the content list to navigate to where you want to go.



Follow this url for setup and startup instructions for Cadence 6.1.6 with TSMC's 90 nm design kit


From time to time problems are discovered and corrected, so checking out this section of the wiki from time to time is adviced:



Creating a library

The first thing to do is to make your own library.

  • In The main Viruoso window, choose Tools->Library Manager.

  • The window Library Manager is opened: Choose File->New->Library.

  • The window New Library is opened: Write a suitable name for the new library and press OK.
    • In this guide the library is called inv.
  • The Window Technology File for New Library opens: Choose Attach to an existing techfile and press OK. Take note that this window sometimes opens behind the Library Manager window.


  • The Window Attach Design Library to Technology File opens: Choose tsmcN90rf from the Technology Library-menu and press OK. (For other design kits use the appropriate techfile.)


    • The library inv has now been created.

Here is a instruction video on how to do it:
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Creating schematic

  • In Library Manager first choose th library inv and then File->New->Cell View
  • The window Create New File opens: Write a suitable name


    • In this guide the cell name is inv
  • The Schematic Editor will now open, if you need to open it again at a later stage, simply double click in the Library view field and the Schematic Editor will automatically open.


Drawing of Schematics

  • To fetch new components, choose Create->Instance or press i
  • The window Add Instance opens: Press Browse to find available components


  • The window Library Browser opens. Mainly components from the librarys tsmcN90rf and analogLib will be used. tsmcN90rf contains components spesific for the design kit, like transistors, resistors, capacitors and diodes, while analogLib is a general library which is independent of the design kit. In addition there are some libraries that contains standard cells like logical gates, registers, counters, pads and so forth. For starters it is advisable to concentrate on the two first mentioned libraries.
  • In the library tsmcN90rf, category Mosfets_mac choose nch_mac and choose the symbol view. Then place the components in the schematic-window.

If you want to run Monte-Carlo simulations (which you do want) you need to use components with the 'mac' ending, as theese are the components holding the statistical data that is required for that simulation. 
  • Repeat this with the pch_mac and place them as shown in the figure below:
    • nch_mac and pch_mac is respectively nmos-transistor and pmos-transistor with standard threshold voltage.
  • Choose Add->wire (narrow) or press w to draw wire between the components.
  • Choose Add->pin or press p to add pins.
  • The window Add Pin opens: Write IN, OUT, VDD and GND in the field Pin Names and choose respectively Input, Output and inputOutput under the Direction-menu as the pins are placed in the design.
Writing all the pin names in capital letters avoids problems later on in your design.

Image:AddPinIN.png Image:AddPinOut.png

  • Choose Design->Check and Save or press X

Your design should now look like this:

Here is a instruction video on how to do it:
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Creating a Symbol

When you want to simulate your design, it makes sense to make a test bench for the simulation. For the test bench to remain a tidy system you can and should create symbols of your smaller parts.

  • In the Schematic window, chose Create->Cellview->From Cellview
  • The window Cellview from Cellview opens. Choose to generate a symbol from a schematic and press OK


  • The window Symbol Generation Options opens: Chose the placement for the pins in the design. In this instance IN is on the left side, while OUT is on the right side. Both VDD and GND is added to the top here, you normaly want to change GND to the bottom. Press OK


  • The Symbol is generated and the window Virtuoso Symbol Editing opens. You might have to press SHIFT F for the view to refresh. Here you can edit the layout of the symbol if you wish.


  • Chose Design->Check and Save and close the window.

Here is a instruction video on how to do it:
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Setting up a SimCell

  • In Library Manager, chose File->New->Cell View.
  • The window Create New File opens: Write in the name SIM_inv in Cell Name and chose Composer-Schematic from the Tool-menu and press OK

  • The window Virtuoso Schematic Editing opens: Press i and import inv-inv-symbol

In this example we will do a simple transient analysis, where the input IN is switched from logical 0 to logical 1 and the output OUT is observed and plotted. In this design kit the supply voltage (VDD) is 1.2V. First the necessary sources must be applied to the design:

  • Press i and add analogLib-vdc-symbol and analogLib-vpulse-symbol. Also add the global vdd and ground (analogLib-vdd-symbol and analogLib-vss-symbol) and the necessary wires and pin as shown on the figure under.


  • Choose the vdc-symbol and chose Edit->Properties->Objects or press q
  • The window Edit Object Properties opens: Write in 1.2 (tab out of it and the appropriate V will be added automatically) in the field DC voltage and press OK


  • Choose vpulse and press q
  • Fill out as shown in the figure under and press OK


Here is a instruction video on how to do it:
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Transient simulation

  • In the Schematic window, chose Launch->ADE GXL and Create a new view


  • The window ADE GXL Editing opens

Image:ADEGXL Window 616.png

  • Choose Create>Test..., or doubble click on Tests in the Data View field.
  • The window Choosing Design opens. Choose SIM_inv in this case and press OK.

Image:Choose_Design_GXL_616.png Image:ADE_XL_Testeditor_616.png

  • Choose the analysis you want to run by selecting Analysis<Choose. Choose tran under Analysis, write in 1u in the field Stop Time and press OK


  • Choose Outputs->To Be Plotted->Select on Schematic and press on the nodes or nets in the schematic you wish to plot, in this instance net4 (Here we could add a lable on the input node to get a good name.) and OUT.
  • Choose Variables->Copy from Cellview. The variables pulse and width will be added to the simulation window.
  • Choose Variables->Edit.
  • The window Editing Design Variables opens: Write in 200n and 400n for respectively width and period and press Change to change the value. Press OK to exit the window.


  • Close the Test Editor window.

To run the simulation select Run<Single Run, Sweep and Corners or find the green play button and press it.

  • The Simulation starts. To plot the results find the Plot all Waveforms button. You can also set options for automatically plotting your results.
Remember that all schematic has to be saved before running any simulations.
  • After the simulations are done, it can pay off to save the settings for a later occasion: Chose Session->Save State, write in a suitable name in the Save as-field and press OK

Here is a instruction video on how to do it:
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Monte Carlo simulation

To run a Monte Carlo sampling we change the run mode from Single Run... to Monte Carlo Sampling. You find the run mode tab by the mouse cursor in the picture below, or under the Run menu.

We also need to take a looke at the Simulation Options, this menu you find to the right of the run mode menu. Click it and the following menu appears:

Image:Cadence MontCarlo.png

Here we need to check the box for Save Data to Allow Family Plots to get all the runs into the plot. Another thing you can consider is the number of runs you run (Number of Points). If you run a lot of runs it will take a long time even for small circuits. Now all we have to do is run using the green Run Simulation button as we did with the simple simulation in the previous example. And here is a possible resulting plot of the simulation:

Here is a instruction video on how to do it:
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Corner simulation

(This part is different for the AMS process. There is a separate tool in that kit to generate the 'corners.sdb' file in the kit. See here how its done here: /projects/nanos/resources/AMS_OPTO/UsageAMScorners.pdf)

To start a Corner simulation we set the run mode back to Single Run, Sweeps and Corners. On the left side of the window wi press the pluss in front of the Corners tab and Click on the Click to add corner option.

Then the following window pops up:

Image:Cadence 616 Corner setup.png

If you press the icon in the top left corner you can load some basic corners.

Image:Cadence 616 Load Corners.png

Select the file corners.sdb from the root of your cadence setup. Now you can run the cornersimulation by pressing the green Run Simulation button. And here is a possible result:

This example shows only the very basic corners. You have the option of course to add a lot more corners.

Here is a instruction video on how to do it:
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Using variables

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DC simulation

  • The steps to run a DC analysis is similar to the transient setup shown above
  • One can either use the "vpulse" as shown above or switch it for "vdc" from the same library as source.
  • Choose the source and press "q"
  • The window Edit Object Properties opens: Enter Vin in the field DC voltage and press OK. "Vin" is a variable name, that you can choose freely.
  • Back in "Analog Enviroment" choose "Variables->Copy From Cellview",
  • Choose Analyses->Choose and the window "Choosing Analyses" opens. Pick "dc" under "Analysis" and set "Sweep Variable" to "Design Variable" and choose "Vin".
  • For "Sweep Range" set "Start", "Stop" and for instance "Number of Steps".


  • Back in "Analog Environmnet" use the buttom marked with "x y z" and give "Vin" some random value (e.g. 0).
  • Choose the signals to be plotted by "Outputs->To Be Plotted->Select On Schematic". These are now plotted against "Vin". If you click on a wire, you get a voltage. If you click on a terminal on a component, you get a current.
  • With "Tools->Result Browser.." one can choose voltages and currents that can be exported to Matlab.

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Power Consumption

To find the power consumption of the device, there are several roads, one is outlined below. Step one: Before simulating the design, ensure pwr is saved, under: "Outputs->Save All...".

After simulation, from the calculator, find the browser: calculator->Tools->Browser

Go into the "tran" folder in the Browser that pops up (this used to be tran.tran, for any oldtimers out there).

Here, you can select "\:pwr", but this gives you the power consumption of the entire testbench, which might not be a good idea if you simulate your device with extra components for shaping and load. Select instead the instance that you are testing, in these images, this is "I3". The following image compares the power consumed by the entire testbench and only the instance of interest ("I3.pwr").

To avoid repeating this step every time you re-simulate the design, right click the pwr signal of interest and select the calculator

You will then get the text "getData("I3.pwr" ?result "tran") in the calculator window. Now you can also integrate the power to obtain the consumed energy by using the calculator command "iinteg". To avoid repeating these steps when the design is re-simulated, go back to the ADE-L window, choose "Outputs -> Setup...", from this dialog, press the Calculator button "Get Expression", (optionally give the expression a name) and press Add. This last step is slightly different (and simpler) in ADE XL, but follows the same pattern.

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Creating the Layout

There are two main ways to start making your layout, either similar to how you started the schematic:

In Library Manager first choose "your_lib" and then choose File->New->Cell view
The window New File opens: Write the correct name, in this instance inv, choose layout from the Type-menu and in the Application-menu choose one of the Layout tools (L, XL or GXL) then press OK

This way continues further down on this page: Manual

Both ways has it's pros and cons. Manual will probably give you more knowledge, and is necessary if you want full control on analog parts of your design for instance.

Auto generating Layout

The other way is a bit more automatic:

From the Schematic XL editor you can launch the Layout GXL tool from the menu ->Launch-Layout GXL

File:Cadence616 creating new layout.png

Make sure you create a new Layout.

File:Cadence616 creating new layout2.png

To get the Layout going we can now import the layout views from our Schematic using the menu ->Connectivity-Generate-All from Source.... Then this window pops up:

File:Cadence 616 Generate Layout 1.png

This first tab is usually OK to leave as it is, but the second tab you need to get right, or you could just as well do this by hand:

File:Cadence 616 Generate Layout 2.png File:Cadence 616 Generate Layout 3.png

We need to make sure all the pins are generated in the right layer. In our case metal 1 or M1. It also needs to be in the pin layer. When we were drawing our layout we were using the drawing layer, or the drw layer. And secondly we need to get the Pin Label correct:

File:Cadencen 616 Set Pin Label Text Style.png

Here it is a good idea to change the Height to 0.1 for small designs like this example. The critical thing however to get right is to set the Layer name and Layer Purpose to Same As Pin. The result should be something like this:

If we move things around a bit (just mouse click and move), and press Shift F to see all the structures, and right-click on each of the transistors to get the rotate option and rotate both left or use the middle mouse button for rotation, and put the two transistor right across from one another and finally press f to "fit" everything we get something like this:

File:Cadence 616 Layout GXL orgenizing.png

By selecting one of the transistors, and pressing q to edit the instance you will get up this window:

File:Cadence 616 Layout editing.png

In the Parameter-tab we are interested in adding a contact for our gate and a contact to the body, bodytie. We are now ready to draw the metal lines to connect the transistors. A good tip here is to cross of the Used box in the Layers window on the right side. If we do so we only work with the already used layers, which in this case is what we want. Select the M1 - drw-layer. Then make sure you have the main window active by clicking on an empty space inside there. You can now draw paths by clickin the short cut p for path or go through the menu ->Create-Wiring-Wire. Start a wire by clicking the mouse, and end it by pressing enter. Then place the Pins on their places by moving them one at the time. Changing the options as shown in the picture and the other instructions should give you the following result:

File:Cadence 616 Layoute GXL 2.png

You should now be able to start running DRC and LVS checks on this design.

Here is a instruction video on how to do it:
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Not so high res

Manual generating Layout

  • In the window Virtuosos Layout Editing the drawing is done.
  • In the layout window, press i. Add tsmcN90rf-nch_mac-layout and cmosN90-pch_mac-layout.
    • press shift-f to see all the layers.
  • Place the components and draw the connections as shown under.
  • Add contacts to power and ground by pressing q and edit the parameters of the transistors as shown above.
    • Place as in the figure under.
  • Add pins
    • Choose Create->Pin or press Ctrl-p
    • The window Create Symbolic Pin opens: Write in Vin, Vout, vdd and gnd and the field Terminal Names
    • Choose sym pin under Mode
    • Cross of for Display Pin Name and press on Display Pin Name Options
    • The window Pin Name Display opens: Cross of for Pin Layer under Layer and press OK
    • Choose the correct pin under I/O Type: vdd and gnd are inputOutput.
    • Place the pins on the correct net. The name on the pin must be placed one the pin itself and must be of the same layer as the pin itself. This should be in order if the tutorial is followed.
  • Some tips:
    • Choose first the correct layer in the 'LSW-window
      • PO-drawing is chosen to draw poly-silicon (the gate)
      • M1-drawing, M2-drawing etc. is chosen to draw metal layer 1,2 etc.
      • NW-drawing is chosen to draw NWELL
      • NP-drawing is chosen to draw N-doped poly/substrate
      • PP-drawing is chosen to draw P-doped poly/substrate
    • Press r to draw a rectangle
    • Press p to draw a path
    • Press m to move
    • Press c to copy
    • Press q to change
  • Through trial and error you will learn more functions, and the layout face itself will go faster. For large/complex layouts it may be advisable to become familier with Layout XL.
  • During this phase it is also possible to test if the design rules are maintained. Go to DRC

The result should be the same as above.

Image:Cadence 616 Layoute GXL 2.png

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Generating contacts or Vias

If you press o or use the menu option Create->Via the window below will pop up.

File:Cadence 616 Create Via.png

The metal to metal vias Mx_M(x-1)are quite self explanatory, and also the metal one to poly M1_PO. But where are the two vias going down to the to different diffusions we have, N+ and P+? They are the same contact, M1_OD. They become different dependent on whether they are enclosed by NP or PP.

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Generating Guard-rings

There is also a tool to create guard-rings. This is invoced by pressing SHIFT-G, or found via the menu Create->MPP Guard Ring. It is wise to create guard rings to separate blocks of your design from one another, and it is also a good way to prevent LUP-errors in you final verification steps for a production ready chip.

File:Cadence 616 Guad Ring.png

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Design Rule Checker (DRC)

DRC is run to check that all the design parameters are adhered to.

  • In the layout window, chose ->Calibre-Run DRC
  • Two windows are opened, Load Runset File and Calibre Interactive - nmDRC.

File:Cadence 616 RunsetDRC.png

  • In Load Runset File choose the run-file you have in your cadence directory/Calibre/drc/runset_DRC, then press OK
    • Note that the runset and rule file is not the same thing.
  • In Calibre Interactive - nmDRC, press Run DRC [sic]

File:Cadence616 Calibre DRC.png

  • DRC is run, and at the end of the run a report of any errors will appear.
  • Documentation of design rules are available from the group engineer. Some trial and error can also go a long way in determining what the various error messages means. Some are self evident, while others are more cryptic.

Here is an instruction video on how to do it:
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Design Rule Checker - Antenna check and full chip DRC

DRC is run to check that all the design parameters are adhered to.

  • In the layout window, chose Calibre-Run DRC
  • Two windows are opened, Custumization Settings and Calibre Interactive - DRC
  • In Customization Settings press OK
  • In Calibre Interactive - DRC, change the the Calibre-DRC Rules File to calibreAntennadrc_cgi. Press Run DMC [sic]
  • DRC is run, and at the end of the run a report of any antenna errors will appear.
  • In the design kit for the 90nm ST process for instance, we do not have the full layout of the PADs. This can lead to problems with finding all the antenna errors. A way to provoke this error is to add a contact from metal 2 to 5 with 6*12 contacts (which is the number of contacts added in the PAD) before running this test. Remember to remove any unnecessary structures from the design befor turning it in.
  • Documentation of design rules are avaliable from the group engineer. Some trial and error can also go a long way in determining what the various error messages means. Some are self evident, while others are more cryptic.

Here is an instruction video on how to do it:
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Layout versus Schematic (LVS)

When DRC is run without errors, you can run a LVS. As the name indicates, the schematic will be compared to the layout, and any mismatch will be reported. For this to work in it is absolutely critical that the Pins are made correct. See the layout section for instructions.

  • In the layout window, choose Calibre->Run LVS
  • Two windows are opened, Load Runset File and Calibre Interactive - nmLVS
  • In Load Runset File do as you did when you ran the DRC, load the runset file from your own cadence folder/Calibre/lvs/reunset_LVS, then press OK.
  • In Calibre Interactive - LVS, press Run LVS

  • LVS is run and at the end of the run a report over any errors will appear. If the result is as we want it we get a result as shown under:

Here is an instruction video on how to do it:
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Simulating on layout

Extracting parasites (PEX)

When the DRC and LVS are error free we are ready for extracting the parasitics from the layout so we can include them in our simulations. We start of from our Layout and choose from the menu->Calibre-Run PEX

The window Load Runset File pops up as before with the DRC and LVS. As before choose the runset file runset_PEX in your Calibre folder located in your Cadence folder.

File:Cadence 616 PEX load runset.png

The runset file gives you a setup that works, but as you work your way through various designs you might want to change some things. In the Input section it is usually a good idea to export the Layout from the layout view, and for the Netlist to export it from the schematic viewer. In the Output section both R, C and L is extracted. For larger systems this could lead to long simulation times, so you might extract less while you are just fiddling around, and save the long simulation until you think things are working. There are also advanced options under "PEX options" (enable in the setup menu) and "Netlist" -> "Reduction and CC" for further simplification.

File:Cadence 616 Calibre PEX.png

For designs using RF components, the parasitics are already included in the model and so LVS must be told to ignore the parasitics to avoid double counting. This can be achieved with the hcells options, by creating a text file with the format

cell_name cell_name

An example hcell file is shown in the image below:


When you are happy with your setup, run the extraction by pressint the Run PEX button. Then the Calibre Viev Setup window will pop up. In this window you have to take note of a few thing that needs to be correct:

The Cellmap File: needs to be ./Calibre/rcx/calview.cellmap
The Cellview Type: needs to be Schematic
The Device Placement: should be Arrayed
And finally you should Open Calibre CellView in read mode to verify that you got the extraction result you expected.

File:Cadence 616 Calibre PEX View Setup.png

If your calview.cellmap file is missing some of the devices you are using you will get an extra dialog asking you to help with sorting out the unknown devices. Map Calibre Device. This window wants you to map device pins from already existing cells in the library. For example, if the specified device is nch_mac: Click “Browse”, find the nch_mac symbol in the tsmcN90rf library, and click on Auto Map Pins. Click OK. An identical window pops up and asks you to perform the same procedure again. Repeat the process for all the other devices you have used in your design.

Then the new Calibre view we made opens and we can se the result:

We need to zoom in a bit to see the various devices that was extracted.

Here is an instruction video on how to do it:
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Simulating with the extracted parasites

To simulate on the Parasites we have extracted we need to make a new view in our simulation cell, we are going to make a config view. What this does it enables us to change between the schematic we have of the inverter and the calibre view that contains the inverter and the parasites when we run our simulations. So we select the SIM_inv and select ->File-New...-Cell View

Then this window pops up:

File:Cadence 616 new config.png

Here we want to set the Type to config, and press OK. Then you get the New Configuration window.

File:Cadence 616 PEX New Config.png

Here you start by setting the View: field to schematic and then press the Use Template button. Here you set the Name: field to spectre, and press OK in both windows.

File:Cadence 616 PEX use Template.png

The the Hierarchy Editor window pops up.

What we want to do here is right click in the inv line and under the Set Cell View option select calibre. Then youw window should look something like this:

Save and Close this window.

To continue with the simulations it is important that you start from the config' view in, in this case the SIM_inv Cell to get the configuration changes you made. If you start your simulation via the schematic view you will only be simulating on the schematic, not the extracted calibre view. Double clicking on the config view gives you this window:

File:Cadence 616 simulating on the calibre view.png

The top line is for weather you want to open, and possible edit the config. In this case we just want to get the simulation going, so we only select the second line. Press OK. Then the normal schematic editor opens. From here you can open the Analog Design Environment ->Launch-ADE-(your preference (L, XL or GXL)). Choose Open Existing View in the next window and press OK. If your next window looks something like this:

Press OK. Then you get the familiar window from the schematic simulations you have already done.

To check that everything is OK you should visually check that you actually are using the calibre view. You can do that by clicking the (in this case) SIM_inv tab. Then you see the schematic of the simulation cell. By selecting the inv cell and pressing Shift-e you can decend into the cell and things should look something like this:

Zoom in to have a closer look at things if you want. Press Ctrl-e to get back out again. Now everything is OK and you can run simulations just as you did with the schematic. Note that simulating with parasites on large designs will take significantly more time.

Back to the Transient simulation section

Here is an instruction video on how to do it:
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Not so high res

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So, what's next?

You now have all the tools you need to make the core of your chip. It is now you need to think about all the things you have learned through your studies and put it to practical use. You need to think about cross talk, noise, proper grounding, fan in and out and all the other words that perhaps did not mean much when you first heard them. And finally you need to bring in power and input signals from the outside world, and take the resulting signals from your chip out to the world outside.


The PAD-frame is a frame around the entire chip that provides the connection points (bond-PADs) between the core of the chip and the outside world. On the bond pads we can connect a wire (bonding wire) from the chip to a PCB or a (chip)package. The other main purpose of the PAD-frame is to provide ESD-protection for the core. The PADs contains structures that protects the chip from being destroyed due to static electricity for instance.

In the picture you see the bond-PADs on the top, and normal PADs and spacers providing an unbroken ring of metal lines around the rim of the chip to distribute VDD and GND and to protect the chip against ESD events.


The Seal-ring around the chip provides a solid ring of metal around the chip to be used as cutting guides when the whole wafer is diced.

In your Library Manager there is a library called Sealring_for_miniasic. There you can find the seal-rings we usually use for this process. It is needed to use the seal-ring if you want to do a hole-chip DRC with the dummy-filling done. The Seal-ring provides the boundary for the filler-algorithm. You can alternatively set dimensions for the filling function to just check the filling for smaller parts of your design.

Dummy filling

When the design is close to finished it is time to start making it producible. One part of that is to run the antenna DRC check. Another part is to fill the chip with Dummy metal. This is metal that is left floating all over the chip to make sure it is possible to make the next metal layer ontop of the previous one. This section will explain how to do the dummy filling, and doing so will remove the density errors. Any errors remaining in this category will have to be dealt with.

Through this procedure you need to keep a level head, so testing it before you really need to have it working in 10 sec (when the chip deadline approaches) is mandatory.

The short version is like this:

- Put on the seal ring to your finished design.
- Make sure you have calibre in your path by sourcing the .bash_tsmc90nmlp found in your cadence startup directory using the command:
  source CRN90LP_session_IC616
- Copy the two encrypted dummy generating files (*.encrypt) to a new or empty folder:
cp -R /projects/nano/script/dummygenerating/* .
- Make three new libraries
 - One for the Metal fill
 - One for the Poly fill
 - One to put everything together
- If you not already have, make a .gds file of your layout with the export tool
- Put in the gds filename and topcell name in the two files from the beginning in this text
- Use the following command:
   calibre -drc -hier 'one of the two encrypted files'
 - One time for the Metal file/fill, and one time for the Poly file/fill
- Import the two generated files into their respective libraries
 - Change the topcell name or make a copy with a new name.

Put everything together in the last library, your original design with sealring, the metal 
fill and the poly fill. Done like this you should be able to put all the three instances in 
0.0 in your final layout, so that you do not have to do any fine maneuvering with the files 
various instances.

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The long version

1. Start with exporting your full layout, using the export function, and stream the gds out. Using File -> Export -> Stream...

2. Then copy the following files and directories into a separate folder with the following command:

cp -R /projects/nano/script/dummygenerating/* .

This copies two folders containing one file each, one file for the Poly filling, and one for the metal fill.

3. Then copy the gds from step one into each of the folders.

4. In these two files you need to modify the following two lines:

//Change to the right gds file name here:
LAYOUT PATH "Change.gds"
//Give the right topcell name here:

5. Make sure calibre is in your path by running:

source CRN90LP_session_IC616

6. Run the two .encrypt files (One time for the Metal file/fill, and one time for the Poly file/fill, this should take a while (10min))

calibre -drc -hier 'one of the two encrypted files'

7. Import the two generated files into their respective libraries and rename the topcell.

8. Combine the two dummy layouts and your original layout in a new cell. Done like this you should be able to put all the three instances in 0.0 in your final layout, so that you do not have to do any fine maneuvering with the files various instances.

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Helper shell script

Below is a short shell script that can be modified to help with the above process:


if [ $# -ne 1 ];
    echo "Usage:$0 name"
    exit 1

cp -r /projects/nano/script/dummygenerating/ .
cp $name.gds dummygenerating/OD/
cp $name.gds dummygenerating/MET/

source .bash_tsmc90nmlp
cd dummygenerating

cd OD
sed -e 's/"Change/"'$name'/g' $file1 > tmp.tmp
mv tmp.tmp $file1
calibre -drc -hier $file1

cd ../MET
sed -e 's/"Change/"'$name'/g' $file2  > tmp.tmp
mv tmp.tmp $file2
calibre -drc -hier $file2

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When you design a chip that you want to have produced it is important that it is possible to measure or verify the functions you wish to document. Make sure you understand how loading you system with wires and probes will affect you signals even before you start designing your system.

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Bonding diagram

Bonding is the process of connecting the PADs of the chip to PADs in the package or directly to a PCB. For most of you you will bond your chip in a package to make it easier to handle when you get i back from production. It is important to think about the bonding process even during you initial design faces as placement of ground and power supplies and critical signal ways could be the difference between a successful chip or an expensive piece of silicon which you can measure your inputs on your outputs and nothing else.

If you have initiated Cadence before May 20th you need to add this line to your cds.lib file:

DEFINE ep_pack_2012 /ifi/asgard/project0/nanos/referance/cadence616OA_90nmRFLP/ep_pack_2012

You will then get a selection of packages that you can put your design in. Talk to you supervisor regarding package choise as this is critical to maintain you designs performance during measurements/measure ability. If you are delivering a chip through the EUROPRACTICE system you can find the instructions on what you need to do here:

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Making things available for the others

An area is available here: /projects/nanos/designs/ where upon request an area will be made available for you to copy your cells or designs into an area where they will be locked for editing, and where everyone can copy out things they would like to use.

When your area is available you can make a new empty library in that directory, and then copy your design/cells into that directory. A good way to do this is to copy your top-cell to the new area hierarchically, something like this:

File:Cadence 616 copying.png

It is also important to fix all errors in the next window that pops up:

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Synthesis Tutorial

A newer and more updated tutorial about how to synthesis and generate a digital layout in Encounter is available here:


We have used TSMC 90nm standard cells to take the RTL written in VHDL and to generate a layout file that can be ported to Virtuoso.

An older version, but still valid in some conditions. You can find a tutorial on how to do synthesis here:


And in the root there there is a package with some files:


Also libraries that might be useful are available here:


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Other resources

Collection of screen captured tutorials

Collection of useful keyboard shortcuts

Back to the Cadence IC main page

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Personal tools