Cadence-Tutorial-English-cadence 6.1

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This page will give an introduction to the use of Cadence with the STM 90nm design kit. The complete process from startup to simulating on layout wil be presented for a inverter.

Contents

Startup

Follow the url for setup and startup of Cadence 6.1 with STM's 90 nm design kit

Schematic

Creating a library

The first thing to do is to make your own library.

  • In The main Viruoso window, choose Tools->Library Manager.

  • The window Library Manager is opened: Choose File->New->Library.

  • The window New Library is opened: Write a suitable name for the new library and press OK.
    • In this guide the library is called inv.
  • The Window Technology File for New Library opens: Choose Attach to an existing techfile and press OK. Take note that this window sometimes opens behind the Library Manager window.

image:Attatchtoexisting.png

  • The Window Attach Design Library to Technology File opens: Choose tsmcN90rf from the Technology Library-menu and press OK. (For other design kits use the appropriate techfile.)

image:AttachLibrarytoTechnologyLibrary.png

    • The library inv has now been created.

Creating schematic

  • In Library Manager first choose the library inv and then File->New->Cell View
  • The window Create New File opens: Write a suitable name

image:New_File.png

    • In this guide the cell name is inv
  • The Schematic Editor will now open, if you need to open it again at a later stage, simply double click in the Library view field and the Schematic Editor will automatically open.

px800

Drawing of Schematics

  • To fetch new components, choose Create->Instance or press i
  • The window Add Instance opens: Press Browse to find available components

image:AddInstance.png

  • The window Library Browser opens. Mainly components from the librarys tsmcN90rf and analogLib will be used. tsmcN90rf contains components spesific for the design kit, like transistors, resistors, capacitors and diodes, while analogLib is a general library which is independent of the design kit. In addition there are some libraries which starts with CLOCK, COR and IO90, these contains standard cells like logical gates, registers, counters, pads and so forth. For starters it is advisable to consentrate on the two first mentioned libraries.
  • Choose tsmcN90rf-nch_mac-symbol and place the components in the schematic-window.
  • Repeat this with the following symbols and place them as shown in the figure below:
    • tsmcN90rf-pch_mac-symbol
    • analogLib-vdd-symbol
    • analogLib-gnd-symbol
      • nch_mac and pch_mac is respectively nmos-transistor and pmos-transistor with standard threshold voltage.
  • Choose Add->wire (narrow) or press w to draw wire between the components.
  • Choose Add->pin or press p to add pins.
  • The window Add Pin opens: Write Vin and Vout in the field Pin Names and choose respectively Input and Output under the Direction-menu the pins are placed in the design.
  • Choose Design->Check and Save or press X

Image:Inv-skjema.gif

Layout

  • In Library Manager first choose mylib and then choose File->New->Cell view
  • The window Create New File opens: Write the correct name, in this instance inverter, choose Virtuoso from the Tool-menu and press OK
  • Two new windows opens.
    • The window LSW shows all the available layers or materials that one can use to draw structures.
    • In the window Virtuosos Layout Editing the drawing is done.
  • In the layout window, press i. Add cmos090-nsvt-layout and cmos090-psvt-layout.
    • press shift-f to see all the layers.
  • Place the components and draw the connections as shown under.
  • Add contacts to power and ground.
    • Choose Create->Contact or press o
    • The window Create Contact opens: In the Contact Type-menu, choose M1_sub for nmos-transistorer and M1_NW for pmos-transistors.
    • Place as in the figure under.
  • Add pins
    • Choose Create->Pin or press Ctrl-p
    • The window Create Symbolic Pin opens: Write in Vin, Vout, vdd and gnd and the field Terminal Names
    • Choose sym pin under Mode
    • Cross of for Display Pin Name and press on Display Pin Name Options
    • The window Pin Name Display opens: Cross of for Pin Layer under Layer and press OK
    • Choose the correct pin under I/O Type: vdd and gnd are inputOutput.
    • Place the pins on the correct net. The name on the pin must be placed one the pin itself and must be of the same layer as the pin itself. This should be in order if the tutorial is followed.
  • Some tips:
    • Choose first the correct layer in the 'LSW-window
      • PO-drawing is chosen to draw poly-silicon (the gate)
      • M1-drawing, M2-drawing etc. is chosen to draw metal layer 1,2 etc.
      • NW-drawing is chosen to draw NWELL
      • NP-drawing is chosen to draw N-doped poly/substrate
      • PP-drawing is chosen to draw P-doped poly/substrate
    • Press r to draw a rectangle
    • Press p to draw a path
    • Press m to move
    • Press c to copy
    • Press q to change
  • Through trial and error you will learn more functions, and the layout face itself will go faster. For large/complex layouts it may be advisable to become familier with Layout XL.
  • During this phase it is also possible to test if the design rules are maintained. Go to DRC

Image:layout-tegne.gif

Simulating

When you want to simulate your design, it makes sense to make a test bench for the simulation.

  • In the Schematic window, chose Design->Create Cellview->From Cellview
  • The window Cellview from Cellview opens. Choose to generate a symbol from a schematic and press OK
  • The window Symbol Generation Options opens: Chose the placement for the pins in the design. In this instance Vin is on the left side, while Vout is on the right side. Press OK
  • The Symbol is generated and the window Virtuoso Symbol Editing opens: Here you can edit the layout of the symbol if you wish.
  • Chose Design->Check and Save and close the window.
  • In Library Manager, chose File->New->Cell View.
  • The window Create New File opens: Write in the name inverter_sim in Cell Name and chose Composer-Schematic from the Tool-menu and press OK
  • The window Virtuoso Schematic Editing opens: Press i and import mylib-inverter-symbol

Transient simulation

  • In this guide we will do a simple transient analysis, where the input Vin is switched from logical 0 to logical 1 and the output Vout is observed and plotted. In this design kit the supply voltage (vdd) is 1V.
  • Fist the necessary sources must be applied to the design.
  • Press i and add analogLib-vdc-symbol and analogLib-vpulse-symbol as shown on the figure under.

Image:sim-skjema.gif

  • Chose the vdc-symbol and chose Edit->Properties->Objects or press q
  • The window Edit Object Properties opens: Write in 1 in the field DC voltage and press OK
  • Chose vpulse and press q
  • Fill out as shown in the figure under and press OK

Image:Sim-objects.gif

  • In the Schematic window, chose Tools->Analog Environment
    • The window Virtuosos Analog Design Environment opens
  • Chose Analysis->Choose
  • The window Choosing Analysis opens: Chose tran under Analysis, write in 1u in the field Stop Time and press OK
  • Chose Outputs->To Be Plotted->Select on Schematic and press on the nodes or nets in the schematic you wish to plot, in this instance Vin og Vout.
  • Chose Variables->Copy from Cellview. The variables pulse and width will be added to the simulation window.
  • Chose Variables->Edit.
  • The window Editing Design Variables opens: Write in 200n and 400n for respectively width and period and press Change to change the value. Press OK.

Image:Sim-vindu.gif

  • Chose Simulation->Run or press the traffic light symbol with the green light.
    • The Simulation starts and plots chosen graphs after the simulation has ended.
  • Remember to save before running the simulation
  • After the simulations are done, it can pay off to save the settings for a later occasion: Chose Session->Save State, write in a suitable name in the Save as-field and press OK

DC simulation

  • The steps to run a DC analysis is similar to the transient setup shown above
  • One can either use the "vpulse" as shown above or switch it for "vdc" from the same library as source.
  • Choose the source and press "q"
  • The window Edit Object Properties opens: Enter Vin in the field DC voltage and press OK. "Vin" is a variable name, that you can choose freely.
  • Back in "Analog Enviroment" choose "Variables->Copy From Cellview",
  • Choose Analyses->Choose and the window "Choosing Analyses" opens. Pick "dc" under "Analysis" and set "Sweep Variable" to "Design Variable" and choose "Vin".
  • For "Sweep Range" set "Start", "Stop" and for instance "Number of Steps".

Image:ChooseAnalysis1.png

  • Back in "Analog Environmnet" use the buttom marked with "x y z" and give "Vin" some random value (e.g. 0).
  • Choose the signals to be plotted by "Outputs->To Be Plotted->Select On Schematic". These are now plotted against "Vin". If you click on a wire, you get a voltage. If you click on a terminal on a component, you get a current.
  • With "Tools->Result Browser.." one can choose voltages and currents that can be exported to Matlab.

Simulating on layout

The procedure is found here: Post Layout Simulation

Verifying

Design Rule Checker

DRC is run to check that all the design parameters are adhered to.

  • In the layout window, chose Calibre-Run DRC
  • Two windows are opened, Custumization Settings and Calibre Interactive - DRC
  • In Customization Settings press OK
  • In Calibre Interactive - DRC, press Run DMC [sic]
  • DRC is run, and at the end of the run a report of any errors will appear.
  • Documentation of design rules are avaliable from the group engineer. Some trial and error can also go a long way in determining what the various error messages means. Some are self evident, while others are more cryptic.

Design Rule Checker - Antenna check

DRC is run to check that all the design parameters are adhered to.

  • In the layout window, chose Calibre-Run DRC
  • Two windows are opened, Custumization Settings and Calibre Interactive - DRC
  • In Customization Settings press OK
  • In Calibre Interactive - DRC, change the the Calibre-DRC Rules File to calibreAntennadrc_cgi. Press Run DMC [sic]
  • DRC is run, and at the end of the run a report of any antenna errors will appear.
  • In the design kit for the 90nm ST process for instance, we do not have the full layout of the PADs. This can lead to problems with finding all the antenna errors. A way to provoke this error is to add a contact from metal 2 to 5 with 6*12 contacts (which is the number of contacts added in the PAD) before running this test. Remember to remove any unnecessary structures from the design befor turning it in.
  • Documentation of design rules are avaliable from the group engineer. Some trial and error can also go a long way in determining what the various error messages means. Some are self evident, while others are more cryptic.

Layout versus Schematic

When DRC is run without errors, you can run a LVS. As the name indicates, the schematic will be compared to the layout, and any mismatch will be reported.

  • In the layout window, choose Calibre->Run LVS
  • Two windows are opened, Custumization Settings and Calibre Interactive - LVS
  • In Custumization Settings press OK
  • In Calibre Interactive - LVS, press Run LVS
  • LVS is run and at the end of the run a report over any errors will appear.
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